 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| RF5188 0 RoHS Compliant & Pb-Free Product Typical Applications * 3V W-CDMA Band 1 Handsets * Multi-Mode W-CDMA 3G Handsets * 3V TD-SCDMA Handsets * Spread-Spectrum Systems 3V 1950MHZ W-CDMA LINEAR POWER AMPLIFIER MODULE Product Description The RF5188 is a high-power, high-efficiency linear amplifier module specifically designed for 3V handheld systems. The device is manufactured on an advanced third generation GaAs HBT process, and was designed for use as the final RF amplifier in 3V W-CDMA handheld digital cellular equipment, spread-spectrum systems, and other applications in the 1920MHz to 1980MHz band (Band 1). The RF5188 has a digital control line for low power applications to lower quiescent current. The RF5188 is assembled in at 16-pin, 3mmx3mm, QFN package. 3.00 Pin 1 ID A 1.45 Pin 1 ID 3.00 1.45 0.28 TYP 0.18 0.05 0.15 C 2 PLCS B 0.15 C 2 PLCS 0.40 TYP 0.20 0.10 M C A B 0.50 TYP 0.203 REF 0.08 C 0.08 C 0.925 0.775 Shaded areas represent pin 1. 0.102 REF Dimensions in mm. C Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS InGaP/HBT ] Package Style: QFN, 16-Pin, 3x3 GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Features * Input/Output Internally Matched@50 * 27.5dBm Linear Output Power VCCBIAS VCC1/IM * 42% Peak Linear Efficiency NC IM 14 13 16 15 * 28dB Linear Gain * -42dBc ACLR @ 5MHz 12 VCC2 11 VCC2 10 VCC2 RF IN 1 GND 2 VMODE 3 Bias VREG 4 * HSDPA Capable 9 RF OUT Ordering Information 3V 1950MHz W-CDMA Linear Power Amplifier Module RF5188PCBA-41X Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com RF5188 5 NC 6 NC 7 NC 8 NC Functional Block Diagram Rev A4 060310 2-1 RF5188 Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT 31dBm) Control Voltage (VREG) Input RF Power Mode Voltage (VMODE) Operating Temperature Storage Temperature Moisture Sensitivity Level (IPC/JEDEC J-STD-20) Rating +8.0 +5.2 +3.9 +10 +3.9 -30 to +110 -40 to +150 MSL 2 @ 260 Unit V V V dBm V C C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter Specification Min. Typ. Max. Unit Condition T=25oC Ambient, VCCBIAS =3.4V, VCC =3.4V, VREG =2.8V, VMODE =0V, and POUT =27.5dBm for all parameters (unless otherwise specified). Modulation is 3GPP 3.2 03-00 DPCCH+1DPDCH. High Gain Mode (VMODE Low) Operating Frequency Range Linear Gain Harmonics Maximum Linear Output Linear Efficiency Maximum ICC ACLR1 @ 5MHz ACLR2 @ 10MHz Input VSWR Output VSWR Stability Ruggedness Noise Power 1920 26 27.5 38 352 1980 32 -10 47 435 -37 -48 6:1 10:1 -150 -133 -140 dBm/Hz dBm/Hz dBm/Hz MHz dB dBm dBm % mA dBc dBc 28.5 f=2fo, 3fo 42 394 -42 -53 1.7:1 No oscillation>-70dBc No damage -50 dBm/Hz -147 -107 dBm/Hz dBm/Hz IM Products IM 5MHz IM 10MHz -31 -41 dBc dBc 2-2 Rev A4 060310 RF5188 Parameter Specification Min. Typ. Max. Unit Condition T=25oC Ambient, VCCBIAS =3.4V, VCC =1.5V, VREG =2.8V, VMODE =2.8V, and POUT =16dBm for all parameters (unless otherwise specified). Modulation is 3GPP 3.2 03-00 DPCCH+1DPDCH. 1920 22 16 18.3 26 21.0 -41 -54 125 2:1 1980 31 25.3 -37 -48 145 6:1 10:1 IM Products IM 5MHz IM 10MHz -31 -41 3.2 0.6 1.5 3.4 4.2 4.2 93 83 3 6 25 0.5 0.5 2.95 3.0 0.5 3.0 dBc dBc V V V mA mA mA uA uS uS uA V V V V V IF offset fO +5MHz with CW signal=-40dBc IF offset fO +10MHz with CW signal=-40dBc MHz dB dBm % dBc dBc mA No oscillation>-65dBc No damage Low Gain Mode (VMODE High) Operating Frequency Range Linear Gain Maximum Linear Output Linear Efficiency ACLR @ 5MHz ACLR @ 10MHz Maximum ICC Input VSWR Output VSWR Stability Ruggedness 105 Power Supply Supply Voltage (VCC1 and VCC2) VCC Bias High Gain Idle Current (ICC1 /ICC2 /ICCBIAS) Low Gain Idle Current (ICC1 /ICC2 /ICCBIAS) VREG Current VMODE Current RF Turn On/Off Time DC Turn On/Off Time Total Current (Power Down) VREG Low Voltage (Power Down) VREG High Voltage (Recommended) VREG High Voltage (Operational) VMODE Voltage VMODE Voltage Low power with DC to DC Converter VMODE =low and VREG =2.8V, VCC =3.4V VMODE =high and VREG =2.8V, VCC =1.5V 70 60 1 250 1.2 2 0.2 0 2.75 2.7 0 2.0 2.8 High Gain Mode Low Gain Mode Rev A4 060310 2-3 RF5188 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pkg Base Function RF IN GND VMODE VREG NC NC NC NC RF OUT VCC2 VCC2 VCC2 NC IM VCC1/IM VCCBIAS GND Description RF input internally matched to 50. This input is internally AC-coupled. Ground connection. For nominal operation (High Power mode), VMODE is set LOW. When set HIGH, devices are biased lower to improve efficiency at lower output levels. Regulated voltage supply for amplifier bias circuit. In power down mode, both VREG and VMODE need to be LOW (<0.5V). No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. RF output. Internally AC-coupled. Output stage collector supply. Please see the schematic for required external components. Same as pin 10. Same as pin 10. No connection. Do not connect this pin to any external circuit. Interstage matching. Connect to pin 15. First stage collector supply and interstage matching. A 4.7F decoupling capacitor may be required. Connect to pin 14. Power supply input for the DC bias circuitry. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. Interface Schematic 2-4 Rev A4 060310 RF5188 Application Schematic VCC BIAS L2 1 nF 10 F VCC 16 15 14 13 RF IN 1 2 12 11 10 Bias 9 RF OUT Matching Component 1 nF Place this component next to RF5188 with minimal trace length to the PA. VMODE 1 nF 3 4 VREG 1 nF 5 6 7 8 VCC BIAS can be connected to VCC; however, VCC must be maintained above 1.5 V. L2 = 8.2 nH and may be needed to provide isolation between VCC1 and VCC2 depending on layout. Circuit Optimization for Various Output Power Requirements Output Power (dBm) 28 27.5 26.5 26 25 Matching Component 12nH N/A 0.5pF 1.0pF 1.5pF Sample Part Number LQG15HN12NJ02D (Murata) GRM1555C1HR50BZ01E (Murata) GRM1555C1H1R0BZ01E (Murata) GRM1555C1H1R5BZ01E (Murata) Typical Efficiency (%) 41 42 42 42 41 Rev A4 060310 2-5 RF5188 Evaluation Board Schematic VCCBIAS VCC1 R1 0 C30 4.7 F R2 DNI C3 1 nF 16 J1 RF IN 50 strip 1 2 VMODE C20 4.7 F VREG C40 4.7 F C2 1 nF P1 P1-1 P1-2 1 2 3 4 5 CON5 VMODE VRE G GND GND GND P2-3 P2-4 P2-1 5 6 7 8 P2 1 2 3 4 5 CON5 VCC2 GND VCC1 VCCBIAS GND 3 Bias 4 9 50 strip J2 RF OUT 10 12 11 C1 1 nF C10 22 F VCC2 15 L2 DNI 14 13 2-6 Rev A4 060310 RF5188 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns for RFMD components are based on IPC-7351 standards and RFMD empirical data. The pad pattern shown has been developed and tested for optimized assembly at RFMD. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. PCB Metal Land Pattern A = 0.64 x 0.28 (mm) Typ. B = 0.28 x 0.64 (mm) Typ. C = 0.78 x 0.64 (mm) D = 0.64 x 1.28 (mm) E = 1.50 (mm) Sq. Dimensions in mm. 1.50 Typ. 0.75 Typ. Pin 16 B Pin 1 C B 0.50 Typ. A A A A E D 0.75 1.00 Typ. Typ. A B B B B Pin 8 0.55 Typ. 0.55 Typ. 0.75 Typ. Figure 1. PCB Metal Land Pattern (Top View) Rev A4 060310 2-7 RF5188 PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. A = 0.74 x 0.38 (mm) Typ. B = 0.38 x 0.74 (mm) Typ. C = 1.60 (mm) Sq. Dimensions in mm. 1.50 Typ. 0.50 Typ. Pin 16 BBBB Pin 1 0.50 Typ. 0.55 Typ. A A A A C A A A A Pin 8 Pin 12 0.75 Typ. 1.50 Typ. BBBB 0.75 Typ. 0.55 Typ. Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. 2-8 Rev A4 060310 |
Price & Availability of RF5188PCBA-41X
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |